MAX14852 Datasheet, PDF (6/22 Pages) Maxim Integrated Products – 2.75kVRMS Isolated 500kbps/25Mbps Full-Duplex

MAX14852/MAX14854
2.75kV_RMS Isolated 500kbps/25Mbps Full-Duplex
RS-485/RS-422 Transceivers
with ±35kV ESD Protection
Switching Electrical Characteristics (MAX14854)
(V_DDA – V_GNDA = 1.71V to 5.5V, V_DDB – V_GNDB = 3.0V to 5.5V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at
V_DDA – V_GNDA = 3.3V, V_DDB – V_GNDB = 3.3V, V_GNDA = V_GNDB, and T_A = +25°C.) (Note 7)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
UNITS
DYNAMIC
Common Mode Transient
Immunity
CMTI
(Note 8)
35
kV/μs
Glitch Rejection
TXD, DE, RXD
10
17
29
ns
DRIVER
Driver Propagation Delay
tDPLH, tDPHL
RL = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
65
ns
Differential Driver Output Skew
|tDPLH - tDPHL|
Driver Differential Output Rise
or Fall Time
tDSKEW
tLH, tHL
RL = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
R_L = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
7
ns
10
ns
Maximum Data Rate
DRMAX
25
Mbps
Driver Enable to Output High
tDZH
RL = 110Ω, C_L = 50pF, Figure 4
80
ns
Driver Enable to Output Low
Driver Disable Time from Low
Driver Disable Time from High
RECEIVER
Receiver Propagation Delay
tDZL
tDLZ
tDHZ
RL = 110Ω, C_L = 50pF, Figure 5
RL = 110Ω, C_L = 50pF, Figure 5
RL = 110Ω, C_L = 50pF, Figure 4
tRPLH, tRPHL
CL = 15pF, Figure 6 and Figure 7
(Note 9)
80
ns
80
ns
80
ns
65
ns
Receiver Output Skew
|tRPLH - tRPHL|
tRSKEW
CL = 15pF, Figure 6 and Figure 7
(Note 9)
7
ns
Maximum Data Rate
DRMAX
25
Receiver Enable to Output High
tRZH
RL = 1kΩ, C_L = 15pF, S2 closed,
Figure 8
Receiver Enable to Output Low
tRZL
RL = 1kΩ, C_L = 15pF, S1 closed,
Figure 8
Receiver Disable Time From Low
tRLZ
RL = 1kΩ, C_L = 15pF, S1 closed,
Figure 8
Mbps
20
ns
30
ns
20
ns
Receiver Disable Time From High
tRHZ
RL = 1kΩ, C_L = 15pF, S2 closed,
Figure 8
20
ns
Note 2: All devices are 100% production tested at T_A = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or GNDB), unless otherwise noted.
Note 4: V_LDO max indicates voltage capability of the circuit. Power dissipation requirements may limit V_LDO max to a lower value.
Note 5: ΔV_OD and ΔV_OC are the changes in V_OD and V_OC, respectively, when the TXD input changes state.
Note 6: The short circuit output current applies to the peak current just prior to current limiting.
Note 7: Not production tested. Guaranteed by design.
Note 8: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. CMTI
applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between
GNDA and GNDB. V_CM = 1kV
Note 9: Capacitive load includes test probe and fixture capacitance.
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