MAX14852 Datasheet, PDF (18/22 Pages) Maxim Integrated Products – 2.75kVRMS Isolated 500kbps/25Mbps Full-Duplex

MAX14852/MAX14854
2.75kV_RMS Isolated 500kbps/25Mbps Full-Duplex
RS-485/RS-422 Transceivers
with ±35kV ESD Protection
Layout Considerations
It is recommended to design an isolation, or “keep-out,”
channel underneath the isolator that is free from ground and
signal planes. Any galvanic or metallic connection between
the cable side and UART side will defeat the isolation.
Ensure that the decoupling capacitors between V_DDA and
GNDA and between V_LDO, V_DDB, and GNDB are located
as close as possible to the IC to minimize inductance.
Route important signal lines close to the ground plane to
minimize possible external influences. On the cable side
of the devices, it is good practice to have the bus connec-
tors and termination resistor as close as possible to the
A and B pins.
Extended ESD Protection
ESD protection structures are incorporated on all pins
to protect against electrostatic discharge encountered
during handling and assembly. The driver outputs and
receiver inputs of the devices have extra protection
against static electricity to both the UART side and cable
side ground references. The ESD structures withstand
high-ESD events during normal operation and when pow-
ered down. After an ESD event, the devices keep working
without latch-up or damage.
Bypass V_DDA to GNDA and bypass V_DDB and V_LDO to
GNDB with 0.1μF and 1μF capacitors to ensure maximum
ESD protection.
ESD protection can be tested in various ways. The
transmitter outputs and receiver inputs of the MAX14852/
MAX14854 are characterized for protection to the cable
side ground (GNDB) to the following limits:
●● ±35kV HBM
●● ±18kV using the Air-Gap Discharge method specified
in IEC 61000-4-2
●● ±8kV using the Contact Discharge method specified
in IEC 61000-4-2
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model (HBM)
Figure 11 shows the HBM test model, while Figure 12
shows the current waveform it generates when dis-
charged in a low-impedance state. This model consists of
a 100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. However, it does not
specifically refer to integrated circuits. The devices help in
designing equipment to meet IEC 61000-4-2 without the
need for additional ESD protection components.
The major difference between tests done using the HBM
and IEC 61000-4-2 is higher peak current in IEC 61000-4-2
because series resistance is lower in the IEC 61000-4-2
model. Hence, the ESD withstand voltage measured to
IEC 61000-4-2 is generally lower than that measured
using the HBM.
Figure 13 shows the IEC 61000-4-2 model and
Figure 14 shows the current waveform for IEC 61000-4-2
ESD Contact Discharge Test.
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