DS1683_12 Datasheet, PDF (6/21 Pages) Maxim Integrated Products – Total-Elapsed-Time and Event Recorder with Alarm

DS1683
Total-Elapsed-Time and Event Recorder with Alarm
When the contents of the ETC and Event Counter registers
match or exceed their programmable alarm limits, the
ALARM pin can be driven to its active state as set by the
polarity bit, ALRM POL, located in the Configuration regis-
ter. Each of the alarm limits has an enable bit that should
be used to determine whether or not the ALARM pin
should be activated when the alarm conditions are met.
The DS1683 has an internal, low-temperature-coefficient,
RC-based oscillator that is started on power-up. The
DS1683 uses this RC time base to increment the ETC
register in 250ms increments while the EVENT pin is held
high. When the EVENT pin is driven low, the ETC register
ceases to increment.
EVENT Pin
The DS1683 monitors the state of the EVENT pin to
determine when an event occurs. When the pin is pulled
high, the ETC and Event Counter values are transferred
from shadowed EEPROM to SRAM. While the EVENT pin
is held high, the value of the ETC SRAM begins incre-
menting once every 250ms. Incrementing the ETC SRAM
value while EVENT is high allows the device to increment
the ETC value without contributing to EEPROM wear out.
When the EVENT pin falls to a logic 0, the Event Counter
SRAM value increments by a value of one. Also at this
time the ETC stops accumulating time. The values of
the EVENT and ETC Counter SRAM locations are then
stored in the ETC and EVENT Shadowed EEPROM array.
The EVENT input is deglitched (t_G) to prevent short noise
spikes from triggering an event.
While the EVENT pin is high, the I²C bus is unavailable
for write commands, though read commands can still be
executed. When the EVENT pin transitions low, I²C com-
munication is unavailable for t_W (EEPROM write time),
after which I²C writes are possible. However, if an I²C
write operation is underway, and the EVENT pin transi-
tions low to high, this operation is interrupted so that the
ETC and Event Counter registers can be updated. So it
is important to terminate all I²C write transactions before
transitioning the level on the EVENT pin.
An I²C read command can be performed regardless of
the state of the EVENT pin. On a low-to-high transition
of the EVENT pin, the I²C read command is allowed to
complete. However, it is strongly recommended that all
I²C communication be terminated before transitioning
the level on the EVENT pin.
When the EVENT pin is high and the device detects a
START signal on the I²C bus, a snapshot of the data
Maxim Integrated
in the ETC and Event Counter SRAM is made available
on the I²C bus. When the EVENT pin is low and the
device detects a START signal on the I²C bus, data is
transferred from the ETC and Event Counter shadowed
EEPROM bank memory.
Elapsed Time Counter (ETC)
Register
The Elapsed Time Counter (ETC) register is a 32-bit value
that holds time in quarter-second resolution. The ETC
register consists of 4 bytes of memory in the memory
map. Once the counter reaches FFFFFFFFh, counting
stops. The ETC register is backed by 4 banks of shad-
owed EEPROM, which allow for 200k+ write cycles to
occur before a wearout condition. When an I²C read
occurs while the EVENT pin is high, a snapshot of the
value from the ETC SRAM is made available for the I²C
bus. When the EVENT pin is logic 0, I²C reads take data
from the shadowed EEPROM ETC bank memory.
On power-on reset (POR), the ETC value stored in the
shadowed EEPROM bank memory is loaded into the ETC
SRAM location (Figure 1). This also happens when a low-
to-high transition occurs on the EVENT pin, or when an
I²C write to the ETC register occurs. When data is written
to the ETC register, the value is stored in the shadowed
EEPROM bank memory and also in the corresponding
ETC SRAM location. This data is transferred after the
STOP of the I²C command.
1
VCC
EVENT
PIN
1
2
1
I²C
WRITE COMMAND TO
ETC OR EVENT REGISTERS
1 SHADOWED EEPROM IS WRITTEN TO SRAM
2 SRAM IS WRITTEN TO SHADOWED EEPROM
Figure 1. Data Transfer Between Nonvolatile and Volatile
Memory Types
  6