DS1683_12 Datasheet, PDF (17/21 Pages) Maxim Integrated Products – Total-Elapsed-Time and Event Recorder with Alarm

DS1683
Total-Elapsed-Time and Event Recorder with Alarm
I²C Serial Interface Description
I²C Definitions
The following terminology is commonly used to
describe I²C data transfers. See Figure 7 and the
I²C AC Electrical Characteristics table for additional
information.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. Depending on the
device, when the bus is idle it initiates a low-power
mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs
are commonly used during read operations to identify
a specific memory address to begin a data transfer.
A repeated START condition is issued identically to a
normal START condition.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into
the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses including when it is reading bits from the
slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device performs
a NACK by transmitting a one (done by releasing SDA)
during the 9th bit. Timing (Figure 7) for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
SDA
tBUF
tF
tLOW
SCL
tHD:STA
STOP START
tHIGH
tR
tHD:DAT
tSU:DAT
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 7. I²C Timing Diagram
Maxim Integrated
tHD:STA
tSU:STA
REPEATED
START
tSP
tSU:STO
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