MAX11359A_12 Datasheet, PDF (58/67 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
V_REF/GAIN
FULL-SCALE TRANSITION
V_REF
1 LSB = _{(GAIN x 65,536)}
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
0123
INPUT VOLTAGE (LSB)
65,533 65,535
Figure 20. ADC Unipolar Transfer Function
• With the SLEEP or SLEEP function deasserted on
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
• With the SLEEP or SLEEP function deasserted,
assert WU or WU (wake-up) function on UPIO.
• With the SLEEP or SLEEP function deasserted, the
day alarm triggers.
Wake-Up
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX11359A to exit sleep mode, if in sleep mode. A
wake-up event in normal mode results only in a wake-up
event being recorded in the STATUS register.
RESET
The RESET output pulls low for any one of the following
cases: power-on reset, DVDD monitor trips and RSTE =
0, watchdog timer expires, crystal oscillator is attached,
and 32kHz clock not ready.
The RESET output can be turned off through the RSTE
bit in the PS_VMONS register, causing DVDD low sup-
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
µCs that operate with V_DVDD < 1.8V.
Driving UPIO Outputs to AVDD Levels
UPIO outputs can be driven to AVDD levels in systems
with separate AVDD and DVDD supplies. Disable the
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the system’s analog
58
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
V_REF/GAIN
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1 LSB =
V_REF
(GAIN x 65,536)
x
2
V_REF/GAIN
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
-32,768 -32,766
-1 0 +1
INPUT VOLTAGE (LSB)
+32,765 +32,767
Figure 21. ADC Bipolar Transfer Function
MAX11359A
DAC A
FBA
OUTA
Figure 22. DAC Unipolar Output Circuit
supply to AVDD and CPOUT. Setting UPIO outputs to
drive to CPOUT results in AVDD-referenced logic levels.
Supply Voltage Measurement
The AVDD supply voltage can be measured with the
ADC by reversing the normal input and reference sig-
nal s. The REF voltage is applied to one multiplexer
input, and AGND is selected in the other. The AVDD
signal is then switched in as the ADC reference voltage
and a conversion is performed. The AVDD value can
then be calculated directly as:
V_AVDD = (V_REF x Gain x 65536)/N
where V_REF is the reference voltage for the ADC, Gain
is the PGA gain before the ADC, and N is the ADC
result. Note the AVDD voltage must be greater than the
gained-up REF voltage (V_AVDD > V_REF x Gain). This
measurement must be done in unipolar mode.
Maxim Integrated