MAX11359A_12 Datasheet, PDF(35/67 Page) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

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MAX11359A_12 Datasheet, PDF (35/67 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

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MAX11359A

16-Bit Data-Acquisition System with ADC, DAC,

UPIOs, RTC, Voltage Monitors, and Temp Sensor

ADC Register (Power-On State: 0000 0000 0000 00XX)

MSB

ADCE

STRT

BIP

POL

RATE<2:0>

CONT

MODE<2:0>

ADCREF

LSB

GAIN<1:0>

The ADC register configures the ADC and starts

a conversion.

ADCE: ADC power-enable bit. ADCE = 1 powers up

the ADC, and ADCE = 0 powers down the ADC.

STRT: ADC start bit. STRT = 1 resets the registers

inside the ADC filter and initiates a conversion or cali-

bration. The conversion begins immediately after the

16th ADC control bit is clocked by the rising edge of

SCLK. The initial conversion requires four conversion

cycles for valid output data. If CONT = 0 when STRT is

asserted, the ADC stops after a single conversion and

holds the result in the DATA register. If CONT = 1 when

STRT is asserted, the ADC performs continuous conver-

sions at the rate specified by the RATE<2:0> bits until

CONT is deasserted or ADCE is deasserted, powering

down the ADC. The STRT bit is automatically deasserted

after the initial conversion is complete (four conversion

cycles; the ADC status bit ADD in the STATUS register

asserts.) The current ADC configurations are not affect-

ed if the ADC register is written with STRT = 0. This

allows the ADC and mux configurations to be updated

simultaneously with the S bit in the MUX register.

BIP: Unipolar/bipolar bit. Set BIP = 0 for unipolar mode

and BIP = 1 for bipolar mode. Unipolar-mode data is

unsigned binary format and bipolar is twoâs complement.

See the ADC Transfer Functions section for more details.

POL: Polarity flipper bit. POL = 1 flips the polarity of the

differential signal to the ADC and the input to the signal-

detect comparator (SDC). POL = 0 sets the positive mux

output to the positive ADC and SDC inputs, and the neg-

ative mux output to the negative ADC and SDC inputs.

POL = 1 sets the positive mux output to the negative

ADC and SDC inputs, and the negative mux output to

the positive ADC and SDC inputs.

CONT: Continuous conversion bit. CONT = 1 enables

continuous conversions following completion of the first

conversion or calibration(s) initiated by the STRT or S

bit. Set CONT = 0 while asserting the STRT bit, or prior

to asserting the S bit to perform a single conversion or to

prevent conversions following a calibration. Set CONT =

0 to abort continuous conversions already in progress.

When the ADC is stopped in this way, the last complete

conversion result remains in the DATA register and the

internal ADC state information is lost. Asserting the

CONT bit does not restart the ADC, but results in contin-

uous conversions once the ADC is restarted with the

STRT or S bit.

ADCREF: ADC reference source bit. Set ADCREF = 0

to select REF as the ADC reference. Set ADCREF = 1

to select AVDD as the ADC reference. To measure the

AVDD voltage without having to attenuate the supply

voltage, select REF and AGND as the differential inputs

to the ADC, with POL = 0 and while ADCREF = 1.

GAIN<1:0>: ADC gain-setting bits. These two bits

select the gain of the ADC as shown in Table 5.

Table 5. Setting the Gain of the ADC

GAIN SETTING (V/V)

GAIN1

GAIN0

Maxim Integrated

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