MAX1284-MAX1285 Datasheet, PDF (5/15 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
(V_DD = +4.5V to +5.5V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
SCLK Period
t_CP
SCLK Pulse Width High
t_CH
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
t_CL
t_CSS
t_CSH
t_CSO
t_CS1
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse Width High
t_DOH
t_DOV
t_DOD
t_DOE
t_CSW
C_LOAD = 20pF
C_LOAD = 20pF
C_LOAD = 20pF
C_LOAD = 20pF
MIN TYP MAX
156
62
62
35
0
35
35
10
80
10
65
65
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(V_DD = +2.7V to +3.6V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
SCLK Period
t_CP
SCLK Pulse Width High
t_CH
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
t_CL
t_CSS
t_CSH
t_CSO
t_CS1
SCLK Rise to DOUT Hold
t_DOH C_LOAD = 20pF
SCLK Rise to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse Width High
t_DOV
t_DOD
t_DOE
t_CSW
C_LOAD = 20pF
C_LOAD = 20pF
C_LOAD = 20pF
MIN TYP MAX
208
83
83
45
0
45
45
13
100
13
85
85
100
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Tested at VDD = VDD(MIN).
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6: Electrical characteristics are guaranteed from V_DD(MIN) to V_DD(MAX). For operations beyond this range, see Typical
Operating Characteristics.
Note 7: MAX1284 tested with 20pF on D_OUT and f_SCLK = 6.4MHz, 0 to 5V. MAX1285 tested with same loads, f_SCLK = 4.8MHz,
0 to 3V. D_OUT = full scale.
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