MAX1284-MAX1285 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
OUTPUT CODE
11…111
11…110
11…101
FULL-SCALE
TRANSITION
FS = V_REF - 1LSB
1LSB = ^VREF
4096
00…011
00…010
00…001
00…000
0
12 3
INPUT VOLTAGE (LSBs)
FS
FS - 3/2LSB
Figure 10. Unipolar Transfer Function, Full Scale (FS) =
V_REF - 1LSB, Zero Scale (ZS) = GND
SCLK to DOUT valid timing characteristic. Data can be
clocked into the µP on SCLK rising edge.
3) Pull CS high at or after the 15th rising clock edge. If CS
remains low, trailing zeros are clocked out after the
LSB.
4) With CS = high, wait the minimum specified time, t_CS,
before initiating a new conversion by pulling CS low. If
a conversion is aborted by pulling CS high before the
conversion completes, wait for the minimum acquisition
time, t_ACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with three leading zeros and three
trailing zeros.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Two
consecutive 1-byte reads are required to get the full
twelve bits from the ADC. DOUT output data transitions
on SCLK’s rising edge and is clocked into the following
µP on the rising edge.
The first byte contains three leading zeros, and five bits of
conversion result. The second byte contains the remaining
seven bits and one trailing zero. See Figure 11 for con-
nections and Figure 12 for timing.
I/O
SCK
MISO
SS
a) SPI
+3V TO +5V
CS
SCLK
DOUT
MAX1284
MAX1285
CS
SCK
MISO
SS
b) QSPI
+3V TO +5V
CS
SCLK
DOUT
MAX1284
MAX1285
I/O
CS
SK
SCLK
SI
DOUT
c) MICROWIRE
MAX1284
MAX1285
Figure 11. Common Serial-Interface Connections to the
MAX1284/MAX1285
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1284/MAX1285 require 15 clock cycles
from the µP to clock out the 12 bits of data. Figure 13
shows a transfer using CPOL = 0 and CPHA = 1. The
conversion result contains two zeros followed by the 12
bits of data in MSB-first formatted.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
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