MAX1284-MAX1285 Datasheet, PDF (11/15 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
1.50
C_REF = 4.7µF
1.25
1.00
0.75
0.50
0.25
0
0.0001 0.001 0.01 0.1
1
10
TIME IN SHUTDOWN (s)
Figure 7. Reference Power-Up vs. Time in Shutdown
Applications Information
Connection to Standard Interfaces
The MAX1284/MAX1285 serial interface is fully compat-
ible with SPI/QSPI and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 6.4MHz (MAX1284) or
4.8MHz (MAX1285).
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Activate SCLK for a minimum of fifteen clock cycles.
The first two clocks produce zeros at DOUT. DOUT
output data transitions 20ns after the third SCLK rising
edge and is available in MSB-first format. Observe the
CS
1
SCLK
DOUT HIGH-Z
34
8
12
15
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HIGH-Z
A/D STATE
ACQ
HOLD/CONVERT
ACQUISITION
Figure 8. Interface Timing Sequence
CS
SCLK
tt_CCSSOO
t_CSS
t_CL
t_CH
t_CP
DOUT
t_DOH
t_DOE
t_DOV
t_CSW
t_CSH
t_CSI
t_DOD
Figure 9. Detailed Serial-Interface Timing
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