MAX1198 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 3.3V, OV_DD = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V_IN = 2V_P-P (differential with respect to COM), C_L = 10pF at digital outputs, f_CLK = 100MHz, T_A = T_MIN to T_MAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Low Threshold
CLK
V_IL
PD, OE, SLEEP, T/B
0.2 ×
V_DD
V
0.2 ×
OV_DD
Input Hysteresis
V_HYST
Input Leakage
I_IH
I_IL
Input Capacitance
C_IN
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
V_IH = V_DD = OV_DD
V_IL = 0
0.15
V
±20
µA
±20
5
pF
Output Voltage Low
V_OL
I_SINK = -200µA
0.2
V
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
V_OH
I_LEAK
C_OUT
I_SOURCE = 200µA
OE = OV_DD
OE = OV_DD
OV_DD -
V
0.2
±10
µA
5
pF
Analog Supply Voltage Range
Output Supply Voltage Range
V_DD
OV_DD
C_L = 15pF
2.7
3.3
3.6
V
1.7
2.5
3.6
V
Analog Supply Current
I_VDD
Operating, f_{INA & B} = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
80
95
mA
3.2
0.15
20
µA
Output Supply Current
I_OVDD
Operating, f_{INA & B} = 20MHz at -1dB FS
applied to both channels (Note 6)
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
11.5
mA
2
µA
2
10
Analog Power Dissipation
Power-Supply Rejection
TIMING CHARACTERISTICS
PDISS
PSRR
Operating, f_{INA & B} = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Offset, V_DD ±5%
Gain, V_DD ±5%
264
314
mW
10.6
0.5
66
µW
±3
mV/V
±3
CLK Rise to Output Data Valid
Time
t_DO
C_L = 20pF (Notes 1, 7)
6
8.25
ns
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t_ENABLE
t_DISABLE
t_CH
t_CL
Clock period: 10ns (Note 7)
Clock period: 10ns (Note 7)
5
ns
5
ns
5 ±0.5
ns
5 ±0.5
ns
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