MAX1196 Datasheet, PDF (5/23 Pages) Maxim Integrated Products – Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = OV_DD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V_IN = 2V_P-P (differential with respect to COM), C_L = 10pF at digital outputs (Note 5), f_CLK = 40MHz, T_A = T_MIN to T_MAX,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T_A = +25°C.)
PARAMETER
SYMBOL
Input Hysteresis
V_HYST
Input Leakage
I_IH
I_IL
Input Capacitance
C_IN
DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)
Output Voltage Low
V_OL
CONDITIONS
V_IH = V_DD = OV_DD
V_IL = 0
I_SINK = -200µA
Output Voltage High
V_OH
I_SOURCE = 200µA
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Analog Power Dissipation
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
I_LEAK
C_OUT
OE = OV_DD
OE = OV_DD
V_DD
OV_DD
I_VDD
I_OVDD
PDISS
PSRR
Operating, f_INA&B = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Operating, f_INA&B = 20MHz at -1dB FS
applied to both channels (Note 6)
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Operating, f_INA&B = 20MHz at -1dB FS
applied to both channels
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Offset, V_DD ±5%
Gain, V_DD ±5%
t_DOA C_L = 20pF (Notes 1, 7)
MIN TYP MAX UNITS
0.15
V
±20
µA
±20
5
pF
0.2
V
OV_DD -
0.2
V
±10
µA
5
pF
2.7
3
3.6
V
1.7
3
3.6
V
29
36
mA
3
0.1
20
µA
8
mA
3
µA
3
10
87
108
mW
9
0.3
60
µW
±3
mV/V
±3
6
8.25
ns
CLK Fall to CHB Output Data
Valid
t_DOB C_L = 20pF (Notes 1, 7)
6
8.25
ns
Clock Rise/Fall to A/B Rise/Fall
Time
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
t_DA/B
t_ENABLE
t_DISABLE
t_CH
Clock period: 25ns (Note 7)
6
ns
5
ns
5
ns
12.5
±1.5
ns
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