MAX1196 Datasheet, PDF (14/23 Pages) Maxim Integrated Products – Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut down,
these nodes become high-impedance inputs and can be
driven through separate, external reference sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
The MAX1196’s CLK input accepts CMOS-compatible
clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
SNR
=
20 ×
log


2
×
π
×
1
f_IN
×
t_AJ


where f_IN represents the analog input frequency and
t_AJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1196 clock input operates with a voltage
threshold set to V_DD/2. Clock inputs with a duty cycle
other than 50%, must meet the specifications for high
and low periods as stated in the Electrical
Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting valid
CHA/CHB data output. CHA and CHB data are sam-
pled on the rising edge of the clock signal. Following
the rising edge of the 5th clock cycles, the digitized
value of the original CHA sample is presented at the
output, followed one-half clock cycle later by the digi-
tized value of the original CHB sample.
A channel selection signal (A/B indicator) allows the
user to determine which output data represents which
input channel. With A/B = 1, digitized data from CHA is
present at the output and with A/B = 0 digitized data
from CHB is present.
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
t_CLK
t_CL
t_CH
CLK
t_DOB
t_DOA
A/B
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
t_DA/B
D0A/B–D7A/B D0B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
D5A
D5B
D6A
D6B
Figure 3. System Timing Diagram
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