MAX1185_10 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 3V, OV_DD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V_IN = 2Vp-p (differential w.r.t. COM), C_L = 10pF at digital outputs (Note 1), f_CLK = 20MHz, T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
V_DD
OV_DD
I_VDD
I_OVDD
PDISS
PSRR
Operating, f_{INA or B} = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Operating, C_L = 15pF,
f_{INA or B} = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Operating, f_{INA or B} = 7.5MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Offset
Gain
2.7
3.0
3.6
V
1.7
2.5
3.6
V
35
50
mA
2.8
1
15
µA
9
mA
100
µA
2
10
105 150
mW
8.4
3
45
µW
±0.2
mV/V
±0.1
%/V
CLK Rise to CHA Output Data
Valid
t_DOA Figure 3 (Note 5)
5
8
ns
CLK Fall to CHB Output Data
Valid
t_DOB Figure 3 (Note 5)
5
8
ns
Clock Rise/Fall to A/B Rise/Fall
Time
t_DA/B
6
ns
Output Enable Time
t_ENABLE Figure 4
10
ns
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t_DISABLE
t_CH
t_CL
Figure 4
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
1.5
ns
25 ± 7.5
ns
25 ± 7.5
ns
Wake-Up Time
t_WAKE
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
0.51
µs
1.5
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
f_{INA or B} = 7.5MHz at -0.5dBFS
f_{INA or B} = 7.5MHz at -0.5dBFS
f_{INA or B} = 7.5MHz at -0.5dBFS
-70
dB
0.02 ±0.2
dB
0.25
D eg r ees
Note 1: Equivalent dynamic performance is obtainable over full OV_DD range with reduced C_L.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to V_IH, V_IL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.
_______________________________________________________________________________________ 5