MAX11644 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(V_DD = 2.7V to 3.6V (MAX11645), V_DD = 4.5V to 5.5V (MAX11644), V_REF = 2.048V (MAX11645), V_REF = 4.096V (MAX11644), f_SCL =
1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise Time of SCL Signal After
Acknowledge Bit
t_RCL1 Measured from 0.3V_DD - 0.7V_DD
20
160
ns
Fall Time of SCL Signal
t_FCL Measured from 0.3V_DD - 0.7V_DD
20
80
ns
Rise Time of SDA Signal
t_RDA Measured from 0.3V_DD - 0.7V_DD
20
160
ns
Fall Time of SDA Signal
t_FDA Measured from 0.3V_DD - 0.7V_DD (Note 11)
20
160
ns
Setup Time for STOP Condition
t_SU, _STO
160
ns
Capacitive Load for Each Bus Line C_B
400
pF
Pulse Width of Spike Suppressed
t_SP (Notes 10 and 13)
0
10
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
For DC accuracy, the MAX11644 is tested at VDD = 5V and the MAX11645 is tested at VDD = 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V_DD.
When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
ADC performance is limited by the converter’s noise floor, typically 300µV_P-P.
Measured for the MAX11645 as:
⎡
⎢⎡⎣^V_FS
⎣⎢
(3.6V)
−
V_FS (2.7V)⎤⎦
×
2^N
V_REF
⎤
⎥
⎦⎥
(3.6V − 2.7V)
and for the MAX11644, where N is the number of bits:
⎡
⎣⎢⎢⎡⎣^{VFS (5.5V)}
−
V_FS
(4.5V)⎤⎦
×
2^N
V_REF
⎤
⎥
⎦⎥
(5.5V − 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to V_IL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 11: The minimum value is specified at T_A = +25°C.
Note 12: C_B = total capacitance of one bus line in pF.
Note 13: f_SCL must meet the minimum clock low time plus the rise/fall times.
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