MAX11644 Datasheet, PDF (4/21 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1)
(V_DD = 2.7V to 3.6V (MAX11645), V_DD = 4.5V to 5.5V (MAX11644), V_REF = 2.048V (MAX11645), V_REF = 4.096V (MAX11644), f_SCL =
1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
f_SCL
400
kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
t_BUF
1.3
µs
Hold Time for START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t_HD,STA
t_LOW
t_HIGH
0.6
µs
1.3
µs
0.6
µs
Setup Time for a Repeated START
(Sr) Condition
t_SU,STA
0.6
µs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
t_HD,DAT (Note 10)
t_SU,DAT
t_R
Measured from 0.3V_DD - 0.7V_DD
0
100
20 + 0.1C_B
900
ns
ns
300
ns
Fall Time of SDA Transmitting
t_F
Measured from 0.3V_DD - 0.7V_DD (Note 11)
Setup Time for STOP Condition
t_SU,STO
Capacitive Load for Each Bus Line C_B
Pulse Width of Spike Suppressed
t_SP
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C_B = 400pF, Note 12)
Serial-Clock Frequency
f_SCLH (Note 13)
20 + 0.1C_B
0.6
300
ns
µs
400
pF
50
ns
1.7
MHz
Hold Time, Repeated START
Condition
t_HD,STA
160
ns
Low Period of the SCL Clock
High Period of the SCL Clock
t_LOW
t_HIGH
320
ns
120
ns
Setup Time for a Repeated START
Condition
t_SU,_STA
160
ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
t_HD,_DAT (Note 10)
t_SU,_DAT
t_RCL
0
150
ns
10
ns
20
80
ns
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