MAX11600 Datasheet, PDF (5/23 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V_DD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
V_REF = 2.048V (MAX11601/MAX11603/MAX11605), V_REF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, f_SCL =
1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
SYMBOL
t_HD._DAT (Note 12)
t_SU._DAT
t_RCL (Note 13)
CONDITIONS
MIN TYP MAX UNITS
0
150
ns
10
ns
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
t_RCL1 (Note 13)
20
160
ns
Fall Time of SCL Signal
t_FCL (Note 13)
20
80
ns
Rise Time of SDA Signal
t_RDA (Note 13)
20
160
ns
Fall Time of SDA Signal
t_FDA (Note 13)
20
160
ns
Setup Time for STOP Condition
t_SU, _STO
160
ns
Capacitive Load for Each Bus Line C_B
400
pF
Pulse Width of Spike Suppressed
t_SP
0
10
ns
Note 1: The MAX11600/MAX11602/MAX11604 are tested at V_DD = 5V and the MAX11601/MAX11603/MAX11605 are tested at V_DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V_DD.
Note 7: When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an inter-
nal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV_P-P.
Note 10: Electrical characteristics are guaranteed from V_DD(MIN) to V_DD(MAX). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
[ ] ^VFS ^{(3.3V) − V}FS ^(2.7V)
×
2^N
V_REF
3.3V − 2.7V
,
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
[ ] ^VFS ^{(5.5V) − V}FS ^(4.5V)
×
2^N
V_REF
5.5V − 4.5V
,
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12: A master device must provide a data hold time for SDA (referred to V_IL of SCL) to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: C_B = total capacitance of one bus line in pF. t_R, t_FDA, and t_F measured between 0.3V_DD and 0.7V_DD. The minimum value is
specified at T_A = +25°C with C_B = 400pF.
Note 14: f_SCLH must meet the minimum clock low time plus the rise/fall times.
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