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MAX11600 Datasheet, PDF (4/23 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
MAX11601/MAX11603/MAX11605
2.7
3.6
Supply Voltage (Note 10)
VDD
MAX11600/MAX11602/MAX11604
4.5
V
5.5
fSAMPLE =
188ksps
Internal REF, external clock
External REF, external clock
350 650
250
fSAMPLE =
External REF, external clock
110
75ksps
External REF, internal clock
150
Supply Current
IDD
fSAMPLE =
External REF, external clock
8
µA
10ksps
External REF, internal clock
10
fSAMPLE =
External REF, external clock
2
1ksps
External REF, internal clock
2.5
Power-down
1
10
Power-Supply Rejection Ratio
PSRR (Note 11)
±0.25 ±1 LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
µs
Hold Time for START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
tHD.STA
tLOW
tHIGH
tSU.STA
0.6
µs
1.3
µs
0.6
µs
0.6
µs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
tHD.DAT (Note 12)
tSU.DAT
tR
(Note 13)
0
100
20 + 0.1CB
150
ns
ns
300
ns
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
tF
tSU.STO
CB
tSP
(Note 13)
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency
fSCLH (Note 14)
Hold Time (Repeated) START
Condition
tHD.STA
20 + 0.1CB
0.6
160
300
ns
µs
400
pF
50
ns
1.7
MHz
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
tLOW
tHIGH
tSU.STA
320
ns
120
ns
160
ns
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