MAX11600 Datasheet, PDF (14/23 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
11
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A
P OR Sr
NUMBER OF BITS
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
1
7
11
8
1
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A
SETUP OR
CONFIGURATION BYTE
A P OR Sr
NUMBER OF BITS
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
random access memory (RAM). If the scan mode is set
for multiple conversions, they all happen in succession
with each additional result being stored in RAM. The
MAX11600/MAX11601 contain 8 bytes of RAM, the
MAX11602/MAX11603 contain 8 bytes of RAM, and the
MAX11604/MAX11605 contain 12 bytes of RAM. Once
all conversions are complete, the MAX11600–
MAX11605 release SCL, allowing it to be pulled high.
The master can now clock the results out of the output
shift register at a clock rate of up to 1.7MHz. SCL is
stretched for a maximum acquisition and conversion
time of 7.6µs per channel (Figure 10).
The device RAM contains all of the conversion results
when the MAX11600–MAX11605 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF. RAM contents can be read continu-
ously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.
External Clock
When configured for external clock mode (CLK = 1),
the MAX11600–MAX11605 use SCL as the conversion
clock. In external clock mode, the MAX11600–
MAX11605 begin tracking the analog input on the sev-
enth falling clock edge of a valid slave address byte.
One SCL clock cycle later, the analog signal is
acquired and the conversion begins. Unlike internal
clock mode, converted data is available immediately
after the slave-address acknowledge bit. The device
continuously converts input channels dictated by the
scan mode until given a not acknowledge. There is no
need to re-address the device with a read command to
obtain new conversion results (Figure 11).
The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.
The MAX11600–MAX11605 must operate in external
clock mode for conversion rates up to 188ksps.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan-mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF.
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