MAX115-MAX116 Datasheet, PDF(5/14 Page) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs

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MAX115-MAX116 Datasheet, PDF (5/14 Pages) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs

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2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

TIMING CHARACTERISTICS (continued)

(See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25Â°C,

unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Mode 1, Channel 1

Conversion Time

tCONV

Mode 2, Channel 2

Mode 3, Channel 3

Âµs

Mode 4, Channel 4

Mode 1, Channel 1

390

Conversion Rate

Mode 2, Channel 2

Mode 3, Channel 3

218

ksps

152

Mode 4, Channel 4

116

Startup Time

Exiting shutdown

Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = Â±5V (MAX115) or Â±2.5V (MAX116).

Note 2: Integral nonlinearity is the analog valueâs deviation at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: CLK synchronized with CONVST.

Note 4: fIN = 10.06kHz, VIN = Â±5V (MAX115) or Â±2.5V (MAX116).

Note 5: First five harmonics.

Note 6: All inputs except CH1A driven with Â±5V (MAX115) or Â±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digi-

tized.

Note 7: AVDD = DVDD = +5V, AVSS = -5V, VIN = 0V (all channels).

Note 8: Temperature drift is defined as the change in output voltage from +25Â°C to TMIN or TMAX. It is calculated as

TC = [âREFOUT/REFOUT] / âT.

Note 9: See Figure 2.

Note 10: Defined as the change in positive full scale caused by a Â±5% variation in the nominal supply voltage. Tested with one input

at full scale and all others at AGND. VREFIN = +2.5V (internal).

Note 11: Tested with all inputs connected to AGND. VREFIN = +2.5V (internal).

Note 12: The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit

of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.

Note 13: The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the

circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the

120pF capacitor. The time given is the partâs true bus relinquish time, which is independent of the external bus loading capac-

itance.

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