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MAX11129_12 Datasheet, PDF (5/36 Pages) Maxim Integrated Products – 3Msps, Low-Power, Serial 12-/10-Bit,8-/16-Channel ADCs
MAX11129–MAX11132
3Msps, Low-Power, Serial 12-/10-Bit,
8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11131/MAX11132) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
SCLK Fall to DOUT Transition
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
tCP
tCH
tDOT
tDOD
tDOE
tDS
tDH
tCSS
tCSH
tCSW
Externally clocked conversion
CLOAD =
10pF
VOVDD = 1.5V to 2.35V
VOVDD = 2.35V to 3.6V
CLOAD = 10pF, channel ID on
CLOAD = 10pF, channel ID off
CLOAD = 10pF
See Figure 6
CS or CNVST Rise to EOC Low
(Note 6)
tCNV_INT See Figure 7, fSAMPLE = 3Msps
CS Pulse Width
tCSBW
MIN
20.8
40
4
4
4
1
4
1
5
5
TYP
1.7
MAX UNITS
ns
60
%
16.5
ns
15
15
ns
16
ns
14
ns
ns
ns
ns
ns
ns
2.4
Fs
ns
ELECTRICAL CHARACTERISTICS (MAX11129/MAX11130)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Line Rejection
SYMBOL
CONDITIONS
RES
INL
DNL
10 bit
No missing codes
OETC
GETC
(Note 5)
PSR (Note 6)
MIN
TYP
MAX
UNITS
10
Bits
±0.4
LSB
±0.4
LSB
0.3
±1.0
LSB
0.1
±1.2
LSB
±2
ppm/NC
±0.8
ppm/NC
±0.5
LSB
0.2
±1.0
LSB/V
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