MAX1069_10 Datasheet, PDF (5/20 Pages) Maxim Integrated Products – 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP

58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +4.75V to +5.25V, V_DVDD = +2.7V to +5.5V, f_SCL = 1.7MHz (33% duty cycle), f_SAMPLE = 58.6ksps, V_REF = +4.096V, external
reference applied to REF, REFADJ = AVDD, C_REF = 10µF, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
f_SCLH (Note 11)
Hold Time, (Repeated) Start
Condition
t_HD,STA
Low Period of the SCL Clock
High Period of the SCL Clock
t_LOW
t_HIGH
Setup Time for a Repeated
START Condition
t_SU,STA
MIN TYP MAX UNITS
1.7
MHz
160
ns
320
ns
120
ns
160
ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
t_HD,DAT
t_SU,DAT
(Note 9)
t_RCL (Note 10)
0
150
ns
10
ns
10
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
t_RCL1
t_FCL
t_RDA
t_FDA
t_SU,STO
C_B
t_SP
(Note 10)
(Note 10)
(Note 10)
(Note 10)
20
160
ns
20
80
ns
20
160
ns
20
160
ns
160
ns
400
pF
10
ns
Note 1:
Note 2:
Note 3:
Note 4:
DC accuracy is tested at V_AVDD = +5.0V and V_DVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Offset nullified.
One sample is achieved every 18 clocks in continuous conversion mode.
f_SAMPLE
=
⎛ 18 clocks
⎝⎜ f_SCL
+
⎞ ^-1
t_{CONV ⎠⎟}
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11.
t _ACQ
=
2
×
⎛
⎝⎜
1
f_SCL
⎞
⎠⎟
Note 6:
Note 7:
Note 8:
A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
ADC performance is limited by the converter’s noise floor, typically 480µV_P-P.
[ ] ^VFS ^{(5.25V)- V}FS ^{(4.75V) ×}
PSRR =
5.25V - 4.75V
2^N
V_REF
where N is the number of bits (14).
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