MAX1069_10 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP

58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
S
SDA
0
1
SCL
1
2
Figure 9. MAX1069 Slave Address Byte
1
ADD3
ADD2
ADD1
ADD0
R/ W
A
ACKNOWLEDGE
3
4
5
6
7
8
9
S
Sr
SDA
0
0
0
0
1
X
X
X
A
1
2
3
4
5
6
7
8
9
F/S-MODE
HS-MODE
Figure 10. F/S-Mode to HS-Mode Transfer
clock cycle (Figure 10). After the not acknowledge, the
MAX1069 is in HS-mode. The master must then send a
repeated START followed by a slave address to initiate
HS-mode communication. If the master generates a
STOP condition, the MAX1069 returns to F/S-mode.
Data Byte (Read Cycle)
Initiate a read cycle to begin a conversion. A read
cycle begins with the master issuing a START condition
followed by seven address bits and a read bit (R/W).
The standard I²C-compatible interface requires that
R/W = 1 to read from a device, however, since the
MAX1069 does not require setup or configuration, the
read mode is inherent and R/W controls power-down
(see the Internal Reference Shutdown section). If the
address byte is successfully received, the MAX1069
(slave) issues an acknowledge and begins conversion.
As seen in Figure 11, the MAX1069 holds SCL low dur-
ing conversion. When the conversion is complete, SCL
is released and the master can clock data out of the
device. The most significant byte of the conversion is
available first and contains D13 to D6. The least signifi-
cant byte contains D5 to D0 plus two trailing sub bits
S1 and S0. Data can be continuously converted as long
as the master acknowledges the conversion results.
Issuing a not acknowledge frees the bus allowing the
master to generate a STOP or repeated START.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1069 in shutdown. When the
internal reference is used, allow 12ms for the reference
to settle when C_REF = 10µF and C_REFADJ = 0.1µF.
Automatic Shutdown
The MAX1069 automatic shutdown reduces the supply
current to less than 0.6µA between conversions. The
MAX1069 I²C-compatible interface is always active.
When the MAX1069 receives a valid slave address the
device powers up. The device is then powered down
again when the conversion is complete. The automatic
shutdown function does not change with internal or
external reference. When the internal reference is cho-
sen, the internal reference remains active between con-
versions unless internal reference shutdown is requested
(see the Internal Reference Shutdown section).
Internal Reference Shutdown
The R/W bit of the slave address controls the MAX1069
internal reference shutdown. In external reference
mode (REFADJ = AVDD), R/W is a don’t care. In inter-
nal reference mode, setting R/W = 1 places the device
in normal operation and setting R/W = 0 prepares the
internal reference for shutdown.
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