MAX1069_10 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 58.6ksps, 14-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP

58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +4.75V to +5.25V, V_DVDD = +2.7V to +5.5V, f_SCL = 1.7MHz (33% duty cycle), f_SAMPLE = 58.6ksps, V_REF = +4.096V, external
reference applied to REF, REFADJ = AVDD, C_REF = 10µF, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
Digital Supply Voltage
V_AVDD
4.75
5.25
V
V_DVDD
2.7
5.5
V
Internal reference
(powered down
between conversions,
R/W = 0)
f_SAMPLE = 58.6ksps
f_SAMPLE = 10ksps
f_SAMPLE = 1ksps
Shutdown
1.8
2.5
mA
0.7
40
µA
0.4
5.0
Analog Supply Current
I_AVDD
Internal reference
(always on, R/W = 1)
f_SAMPLE = 58.6ksps
f_SAMPLE = 10ksps
f_SAMPLE = 1ksps
Shutdown
1.8
2.5
1.4
mA
1.1
0.4
5
µA
External reference
(REFADJ = AVDD)
f_SAMPLE = 58.6ksps
f_SAMPLE = 10ksps
f_SAMPLE = 1ksps
Shutdown
0.90 1.8
mA
0.36
40
µA
0.4
5
f_SAMPLE = 58.6ksps
Digital Supply Current
I_DVDD
f_SAMPLE = 10ksps
f_SAMPLE = 1ksps
Shutdown
Power-Supply Rejection Ratio
PSRR V_AVDD = 5V ±5%, full-scale input (Note 8)
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
260 400
65
µA
6
0.2
5
2
6
LSB/V
Serial Clock Frequency
f_SCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
t_BUF
1.3
µs
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t_HD,STA
t_LOW
t_HIGH
0.6
µs
1.3
µs
0.6
µs
Setup Time for a Repeated
START Condition (Sr)
t_SU,STA
0.6
µs
Data Hold Time
Data Setup Time
t_HD,DAT
t_SU,DAT
(Note 9)
0
900
ns
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
t_R
(Note 10)
20 +
0.1C_B
300
ns
Fall Time of SDA Transmitting
t_F
(Note 10)
20 +
0.1C_B
300
ns
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
t_SU,STO
C_B
t_SP
0.6
µs
400
pF
50
ns
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