DS1643 Datasheet, PDF (5/17 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

DS1643/DS1643P
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within 1 minute per month at 25C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within 1.53 minutes per month (35ppm) at 25C.
Table 2. Register Map—Bank1
ADDRESS _B7
B₆
B₅
DATA
B₄
B₃
B₂
B₁
B₀ ^{FUNCTION RANGE}
1FFF
————————
Year
00-99
1FFE
X X X —————
Month
01-12
1FFD
X X ——————
Date
01-31
1FFC
1FFB
1FFA
X Ft X X X — — —
X X ——————
X ———————
Day
Hour
Minutes
01-07
00-23
00-59
1FF9
1FF8
OSC ^{— — — — — — —}
W
R
X
X
X
X
X
X
Seconds
Control
00-59
A
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t_AA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (t_CEA) or at output enable access time (t_OEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before t_AA , the data
lines are driven to an intermediate state until t_AA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (t_OH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t_WR prior to the initiation of another read or
write cycle. Data in must be valid t_DS prior to the end of write and remain valid for t_DH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs t_WEZ after WE goes active.
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