DS1643 Datasheet, PDF (4/17 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

Figure 1. Block Diagram
DS1643/DS1643P
DS1643/
DS1643P
Table 1. Truth Table
V_CC
CE ^CE2 OE
WE
V_IH
X
X
X
X
V_IL
X
X
5V 10%
V_IL
V_IH
X
V_IL
V_IL
V_IH
V_IL
V_IH
V_IL
V_IH
V_IH
V_IH
<4.5V >
V_BAT
X
X
X
X
<V_BAT
X
X
X
X
MODE
Deselect
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High Z
High Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Standby
Active
Active
Active
CMOS Standby
Data Retention Mode
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable).
4 of 17