DS1374_10 Datasheet, PDF (5/18 Pages) Maxim Integrated Products – I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output

I²C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
POWER-UP/POWER-DOWN CHARACTERISTICS
(T_A = -40°C to +85°C) (Figure 3)
PARAMETER
SYMBOL
CONDITIONS
V_CC Detect to Recognize Inputs
(V_CC Rising)
V_CC Fall Time; V_PF(MAX) to
V_PF(MIN)
V_CC Rise Time; V_PF(MIN) to
V_PF(MAX)
t_RPU (Note 24)
t_F
t_R
MIN TYP MAX UNITS
250
ms
300
μs
0
μs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: V_BACKUP should not exceed V_{CC MAX} or 3.7V, whichever is greater.
Note 5: The use of the 250Ω trickle-charge resistor is not allowed at V_CC > 3.63V and should not be enabled.
Note 6: Measured at V_CC = typ, V_BACKUP = 0V, register 09h = A5h.
Note 7: Measured at V_CC = typ, V_BACKUP = 0V, register 09h = A6h.
Note 8: Measured at V_CC = typ, V_BACKUP = 0V, register 09h = A7h.
Note 9: SCL only.
Note 10: SDA and SQW and INT.
Note 11: The RST pin has an internal 50kΩ pullup resistor to V_CC.
Note 12: Trickle charger disabled.
Note 13: I_CCA—SCL clocking at max frequency = 400kHz.
Note 14: Specified with I²C bus inactive.
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: WDSTR = 1. BBSQW = 1 is required for operation when V_CC is below the power-fail trip point (or absent).
Note 17: C_B—total capacitance of one bus line in pF.
Note 18: After this period, the first clock pulse is generated.
Note 19: The maximum t_HD:DAT only has to be met if the device does not stretch the low period (t_LOW) of the SCL signal.
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V_IHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 21: A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT ≥ to 250ns must be met. This is
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line t_{R max +} t_SU:DAT = 1000 + 250 = 1250ns before
the SCL line is released.
Note 22: Guaranteed by design. Not production tested.
Note 23: The parameter t_OSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V ≤ V_CC ≤ V_{CC MAX} and 1.3V ≤ V_BACKUP ≤ 3.7V.
Note 24: This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
added to this delay.
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