DS1374_10 Datasheet, PDF (14/18 Pages) Maxim Integrated Products – I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output

I²C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
1 OF 16 SELECT
NOTE: ONLY 1010b
ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
V_CC
TCS_0-3 = TRICKLE CHARGER SELECT
DS_0-1 = DIODE SELECT
TOUT_0-1 = RESISTOR SELECT
R1
250Ω
R2
2kΩ
R3
4kΩ
V_BACKUP
Figure 7. Programmable Trickle Charger
SDA
SCL
START
CONDITION
MSB
1
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
2
6
7
8
9
ACK
Figure 8. I²C Data Transfer Overview
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
1
2
3–7
8
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERED
STOP
CONDITION
OR REPEATED
START
CONDITION
I²C Serial Data Bus
The DS1374 supports the I²C bus protocol. A device
that sends data onto the bus is defined as a transmitter
and a device receiving data is a receiver. The device
that controls the message is called a master. The
devices that are controlled by the master are slaves. A
master device that generates the serial clock (SCL),
controls the bus access, and generates the START and
STOP conditions must control the bus. The DS1374
operates as a slave on the I²C bus. Connections to the
bus are made through the open-drain I/O lines SDA
and SCL. A standard mode (100kHz max clock rate)
and a fast mode (400kHz max clock rate) are defined
within the bus specifications. The DS1374 works in both
modes.
The following bus protocol has been defined (Figure 8):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high can be interpret-
ed as control signals.
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