MAX16046A Datasheet, PDF (46/71 Pages) Maxim Integrated Products – 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 27. RESET Configuration and Dependencies (continued)
REGISTER/
EEPROM
ADDRESS
1Ah
1Bh
BIT RANGE
DESCRIPTION
[0]
RESET DEPENDENCIES
1 = RESET is dependent on MON1
[1]
1 = RESET is dependent on MON2
[2]
1 = RESET is dependent on MON3
[3]
1 = RESET is dependent on MON4
[4]
1 = RESET is dependent on MON5
[5]
1 = RESET is dependent on MON6
[6]
1 = RESET is dependent on MON7
[7]
1 = RESET is dependent on MON8
[0]
1 = RESET is dependent on MON9*
[1]
1 = RESET is dependent on MON10*
[2]
1 = RESET is dependent on MON11*
[3]
1 = RESET is dependent on MON12*
[7:4]
Reserved
*MAX16046A only
Watchdog Timer
The watchdog timer can operate together with or inde-
pendently of the MAX16046A/MAX16048A. When oper-
ating in dependent mode, the watchdog is not
activated until the sequencing is complete and RESET
is de-asserted. When operating in independent mode,
the watchdog timer is independent of the sequencing
operation and activates immediately after V_CC exceeds
the UVLO threshold and the boot phase is complete.
Set r4Dh[3] to ‘0’ to configure the watchdog in depen-
dent mode. Set r4Dh[3] to ‘1’ to configure the watchdog
in independent mode. See Table 28 for more informa-
tion on configuring the watchdog timer in dependent or
independent mode.
Dependent Watchdog Timer Operation
The watchdog timer can be used to monitor μP activity
in two modes. Flexible timeout architecture provides an
adjustable watchdog startup delay of up to 192s, allow-
ing complicated systems to complete lengthy boot-up
routines. An adjustable watchdog timeout allows the
supervisor to provide quick alerts when processor
activity fails. After each reset event (V_CC drops below
UVLO then returns above UVLO, software reboot, man-
ual reset (MR), EN input going low then high, or watch-
dog reset) and once sequencing is complete, the
watchdog startup delay provides an extended time for
the system to power up and fully initialize all μP and
system components before assuming responsibility for
routine watchdog updates. Set r55h[6] to ‘1’ to enable
the watchdog startup delay. Set r55h[6] to ‘0’ to disable
the watchdog startup delay.
The normal watchdog timeout period, t_WDI, begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, t_{WDI_STARTUP} (Figures 6
and 7). During the normal operating mode, WDO
asserts if the μP does not toggle WDI with a valid transi-
tion (high-to-low or low-to-high) within the standard
timeout period, t_WDI. WDO remains asserted until WDI
is toggled or RESET is asserted (Figure 7).
While EN is low, or r55h[7] is a ‘0,’ the watchdog timer is
in reset. The watchdog timer does not begin counting until
the power-on mode is reached and RESET is deasserted.
The watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 8). The watchdog timer will be
held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET is pulsed low
for the reset timeout, t_RP, when the watchdog timer
expires and the Watchdog Reset Output Enable bit
(r55h[7]) is set to ‘1.’ Therefore, WDO pulses low for a
short time (approximately 1μs) when the watchdog timer
expires. RESET is not affected by the watchdog timer
when the Watchdog Reset Output Enable bit (r55h[7]) is
set to ‘0.’
See Table 29 for more information on configuring
watchdog functionality.
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