MAX16046A Datasheet, PDF (18/71 Pages) Maxim Integrated Products – 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Detailed Description
Getting Started
The MAX16046A is capable of managing up to twelve
system voltages simultaneously, and the MAX16048A
can manage up to eight system voltages. After boot-
up, if EN is high and the Software Enable bit is set to
‘0,’ an internal multiplexer cycles through each input. At
each multiplexer stop, the 10-bit ADC converts the
monitored analog voltage to a digital result and stores
the result in a register. Each time the multiplexer finish-
es a conversion (12.45μs max), internal logic circuitry
compares the conversion results to the overvoltage and
undervoltage thresholds stored in memory. When a
conversion violates a programmed threshold, the con-
version can be configured to generate a fault. Logic
outputs can be programmed to depend on many com-
binations of faults. Additionally, faults are programma-
ble to trigger the nonvolatile fault logger, which writes
all fault information automatically to the EEPROM and
write-protects the data to prevent accidental erasure.
The MAX16046A/MAX16048A contain both I²C/SMBus
and JTAG serial interfaces for accessing registers and
EEPROM. Use only one interface at any given time. For
more information on how to access the internal memory
through these interfaces, see the I²C/SMBus-Compatible
Serial Interface and JTAG Serial Interface sections.
Registers are divided into three pages with access con-
trolled by special I²C and JTAG commands.
The factory-default values at POR (power-on reset) for
all RAM registers are ‘0’s. POR occurs when V_CC reach-
es the undervoltage-lockout threshold (UVLO) of 2.85V
(max). At POR, the device begins a boot-up sequence.
During the boot-up sequence, all monitored inputs are
masked from initiating faults and EEPROM contents are
copied to the respective register locations. During boot-
up, the MAX16046A/MAX16048A are not accessible
through the serial interface. The boot-up sequence can
take up to 1.5ms, after which the device is ready for
normal operation. RESET is low during boot-up and
asserts after boot-up for its programmed timeout period
once all monitored channels are within their respective
thresholds. During boot-up, the GPIOs, DACOUTs, and
EN_OUTs are high impedance.
Accessing the EEPROM
The MAX16046A/MAX16048A memory is divided into
three separate pages. The default page, selected by
default at POR, contains configuration bits for all func-
tions of the part. The extended page contains the ADC
conversion results, GPIO input and output registers,
and DAC enable bits. Finally, the EEPROM page con-
tains all stored configuration information as well as
saved fault data and user-defined data. See the
Register Map table for more information on the function
of each register.
During the boot-up sequence, the contents of the
EEPROM (r0Fh to r7Dh) are copied into the default
page (r0Fh to r7Dh). Registers r00h to r0Bh of the
default page contain the DAC output voltage registers,
and are reset to ‘0’s at POR. Registers r00h to r0Eh of
the EEPROM page contain saved fault data.
The JTAG and I²C interfaces provide access to all
three pages. Each interface provides commands to
select and deselect a particular page:
• 98h(I²C)/09h(JTAG)—Switches to the extended
page. Switch back to the default page with
99h(I²C)/0Ah(JTAG).
• 9Ah(I²C)/0Bh(JTAG)—Switches to the EEPROM
page. Switch back to the default page with
9Bh(I²C)/0Ch(JTAG).
See the I²C/SMBus-Compatible Serial Interface or the
JTAG Serial Interface section.
Power
Apply 3V to 14V to V_CC to power the MAX16046A/
MAX16048A. Bypass V_CC to ground with a 10μF capaci-
tor. Two internal voltage regulators, ABP and DBP, supply
power to the analog and digital circuitry within the device.
Do not use ABP or DBP to power external circuitry.
ABP is a 2.85V (typ) voltage regulator that powers the
internal analog circuitry and supplies power to the DAC
outputs. Bypass the ABP output to GND with a 1μF
ceramic capacitor installed as close to the device as
possible.
DBP is an internal 2.7V (typ) voltage regulator.
EEPROM and digital circuitry are powered by DBP. All
push-pull outputs are referenced to DBP. DBP supplies
the input voltage to the internal charge pumps when
the programmable outputs are configured as charge-
pump outputs. Bypass the DBP output to GND with a
1μF ceramic capacitor installed as close as possible to
the device.
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