MAX1242 Datasheet, PDF (4/12 Pages) Maxim Integrated Products – +2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
TIMING CHARACTERISTICS
(V_DD = +2.7V to +5.25V, circuit of Figure 9, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
Acquisition Time
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Low to CS Fall Setup Time
DOUT Rise to SCLK Rise (Note 6)
CS Pulse Width
SYMBOL
t_ACQ
t_DO
t_DV
t_TR
f_SCLK
t_CH
t_CL
t_CS0
t_STR
t_CS
CONDITIONS
CS = V_DD (Note 8)
Figure 1,
C_LOAD = 50pF
MAX124_ _C/E
MAX124_ _M
Figure 1, C_LOAD = 50pF
Figure 2, C_LOAD = 50pF
MIN TYP MAX UNITS
1.5
µs
20
200
ns
20
240
240
ns
240
ns
0
2.1
MHz
200
ns
200
ns
50
ns
0
ns
240
ns
Note 1: Tested at V_DD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nulled.
Note 4: Sample tested to 0.1% AQL.
Note 5: External load should not change during conversion for specified accuracy.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Measured as [V_FS (V_DD(min)) - V_FS (V_DD(max))].
Note 8: To guarantee acquisition time, t_ACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
+2.7V
DOUT
6k
C_LOAD = 50pF
DGND
a) High-Z to V_OH and V_OL to V_OH
Figure 1. Load Circuits for DOUT Enable Time
6k
DOUT
C_LOAD = 50pF
DGND
b) High-Z to V_OL and V_OH to V_OL
+2.7V
DOUT
6k
DOUT
6k
C_LOAD = 50pF
DGND
a) V_OH to High-Z
Figure 2. Load Circuits for DOUT Disable Time
b) V_OLto High-Z
C_LOAD = 50pF
DGND
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