MAX1215N Datasheet, PDF (4/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 250Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV_CC = OV_CC = 1.8V, AGND = OGND = 0, f_SAMPLE = 250MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R_L = 100Ω. Limits are for T_A = -40°C to +85°C, unless otherwise noted. Typical values are at
T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
CONDITIONS
Digital Input-Voltage Low
V_IL
Digital Input-Voltage High
V_IH
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
t_PDL
Figure 5
CLK-to-DCLK Propagation Delay
t_CPDL Figure 5
DCLK-to-Data Propagation Delay t_CPDL - t_PDL Figure 5 (Note 3)
LVDS Output Rise Time
t_RISE
20% to 80%, C_L = 5pF
LVDS Output Fall Time
t_FALL 20% to 80%, C_L = 5pF
Output Data Pipeline Delay
t_LATENCY Figure 5
MIN TYP MAX UNITS
0.2 x AV_CC V
0.8 x AV_CC
V
2.23
ns
3.77
ns
1.47 1.54 1.63
ns
155
ps
145
ps
11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range
AV_CC
1.7
1.8
1.9
V
Digital Supply Voltage Range
Analog Supply Current
OV_CC
I_AVCC
f_IN = 100MHz
1.7
1.8
1.9
V
428
480
mA
Digital Supply Current
Analog Power Dissipation
I_OVCC
P_DISS
f_IN = 100MHz
f_IN = 100MHz
64
74
mA
886
965
mW
Power-Supply Rejection Ratio
(Note 4)
PSRR
Offset
Gain
1.7
mV/V
4.5
%FS/V
Note 1: T_A ≥ +25°C guaranteed by production test, T_A < +25°C guaranteed by design and characterization. Typical values are at
T_A = +25°C
Note 2: Static linearity and offset parameters are computed from an endpoint curve fit.
Note 3: Parameter guaranteed by design and characterization: T_A = -40°C to +85°C.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
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