MAX1215N Datasheet, PDF (15/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 250Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
FS VOLTAGE
vs. ADJUST RESISTOR
1.34
1.32
1.30
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND REFIO INCREASES V_FS
1.28
1.26
1.24
1.22
1.20
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES V_FS
1.18
1.16
1.14
0 100 200 300 400 500 600 700 800 900 1000
FS ADJUST RESISTOR (kΩ)
Figure 6b. FS Adjustment Range vs. FS Adjustment Resistor
Differential, AC-Coupled,
LVPECL-Compatible Clock Input
The MAX1215N dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The pre-
ferred method of clocking the MAX1215N is differential-
ly with LVDS- or LVPECL-compatible input levels. The
fast data transition rates of these logic families minimize
the clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ω reverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16 (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
Transformer-Coupled,
Differential Analog Input Drive
The MAX1215N provides the best SFDR and THD with
fully differential input signals and it is not recommend-
ed to drive the ADC inputs in single-ended configura-
tion. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
SINGLE-ENDED
INPUT TERMINAL
10kΩ
0.1µF
50Ω
510Ω
V_CLK
0.1µF
8
2
7
MC100LVEL16D
3
6
510Ω
4
5
0.01µF
0.1µF
150Ω
0.1µF
150Ω
INP
INN
AV_CC OV_CC
CLKN CLKP
MAX1215N
D0P/N–D11P/N, 0RP/N
12
AGND OGND
Figure 7. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration
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