MAX1215N Datasheet, PDF (12/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 250Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 250Msps
ADC for Broadband Applications
On-Chip Reference Circuit
The MAX1215N features an internal 1.25V-bandgap refer-
ence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the FSR
of the MAX1215N. Bypass REFIO with a 0.1µF capacitor
to AGND. To compensate for gain errors or increase/de-
crease the ADC’s FSR, the voltage of this bandgap refer-
ence can be indirectly adjusted by adding an external
resistor (e.g., 100kΩ trim potentiometer) between
REFADJ and AGND or REFADJ and REFIO. See the
Applications Information section for a detailed description
of this process.
To disable the internal reference, connect REFADJ to
AV_CC. Apply an external, stable reference at REFIO to
set the converter’s full scale. To enable the internal ref-
erence, connect REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1215N with an LVDS- or
LVPECL-compatible clock to achieve the best dynamic
performance. The clock signal source must be of high
quality and low phase noise to avoid any degradation in
the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to 1.15V, accept a
typical 500mV_P-P differential signal swing (Figure 4). See
the Differential, AC-Coupled LVPECL-Compatible Clock
Input section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recom-
mended, the clock inputs also accept a single-ended
input signal.
The MAX1215N also features an internal clock-manage-
ment circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum 20MHz
clock frequency to allow the device to meet data sheet
specifications.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1215N features a differential clock output,
which can be used to latch the digital output data with
an external latch or receiver. Additionally, the clock out-
put can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
3.77ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising (falling) edge of DCLKP
(DCLKN). See Figure 5 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1215N offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OV_CC disables the divide-by-2 mode.
REFT
ADC FULL SCALE = REFT - REFB
REFERENCE
REFB
1V
BUFFER
CONTROL LINE TO
DISABLE REFERENCE BUFFER
AV_CC
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
REFERENCE-
SCALING AMPLIFIER
G
AV_CC / 2
MAX1215N
REFIO
REFADJ*
0.1µF
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY
Figure 3. Simplified Reference Architecture
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