MAX1213_09 Datasheet, PDF (4/19 Pages) Maxim Integrated Products – 1.8V, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV_CC = OV_CC = 1.8V, AGND = OGND = 0, f_SAMPLE = 170MHz, differential sine-wave clock input drive, 0.1μF capacitor on REFIO,
internal reference, digital output pins differential R_L = 100Ω ±1%, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at
T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low
V_IL
Digital Input Voltage High
V_IH
TIMING CHARACTERISTICS
CONDITIONS
MIN TYP MAX UNITS
0.2 x AV_CC V
0.8 x AV_CC
V
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
DCLK-to-Data Propagation Delay
LVDS Output Rise Time
LVDS Output Fall Time
t_PDL
Figure 4
t_CPDL Figure 4
t_PDL - t_CPDL Figure 4 (Note 3)
t_RISE
20% to 80%, C_L = 5pF
t_FALL 20% to 80%, C_L = 5pF
Output Data Pipeline Delay
t_LATENCY Figure 4
1.75
ns
4.95
ns
2.8
3.2
3.6
ns
460
ps
460
ps
11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 4)
AV_CC
OV_CC
I_AVCC
I_OVCC
P_DISS
PSRR
f_IN = 65MHz
f_IN = 65MHz
f_IN = 65MHz
Offset
Gain
1.70 1.80 1.90
V
1.70 1.80 1.90
V
375
425
mA
63
75
mA
788
900
mW
1.8
mV/V
1.5
%FS/V
Note 1: ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range (FSR) is defined as 4095 x slope of the line.
Note 3: Parameter guaranteed by design and characterization: T_A = T_MIN to T_MAX.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
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