MAX1213_09 Datasheet, PDF (12/19 Pages) Maxim Integrated Products – 1.8V, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1213 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of 11 clock cycles.
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input T/B
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compati-
ble input, which allows the user to select the desired
output format. Pulling T/B low outputs data in two’s
complement and pulling it high presents data in offset
binary format on the 12-bit parallel bus. T/B has an
internal pulldown resistor and may be left unconnected
in applications using only two’s complement output for-
mat. All LVDS outputs provide a typical voltage swing
of 0.325V around a common-mode voltage of roughly
1.15V, and must be differentially terminated at the far
end of each transmission line pair (true and comple-
mentary) with 100Ω. The LVDS outputs are powered
from a separate power supply, which can be operated
between 1.7V and 1.9V.
The MAX1213 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital out-
puts should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
CLKN
CLKP
DCLKP
DCLKN
t_AD
N
t_CPDL
N-8
t_PDL
N+1
t_LATENCY
N-7
t_CH
N+8
t_CL
N+9
N
t_CPDL - t_PDL
N+1
D0P/N–
D11P/N
N-8
N-7
N-1
N
N+1
ORP/N
t_CPDL - t_PDL~ 0.4 x t_SAMPLE WITH t_SAMPLE = 1/f_SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
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