MAX1213_09 Datasheet, PDF (10/19 Pages) Maxim Integrated Products – 1.8V, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
CLKP
CLKN
INP
INN
CLKDIV
CLOCK-
DIVIDER
CONTROL
INPUT
BUFFER
CLOCK
MANAGEMENT
T/H
2.2kΩ 2.2kΩ
COMMON-MODE
BUFFER
REFERENCE
12-BIT PIPELINE
QUANTIZER
CORE
LVDS
DATA PORT
12
MAX1213
DCLKP
DCLKN
D0P/N–D11P/N
ORP
ORN
Figure 1. Simplified MAX1213 Block Diagram
REFIO REFADJ
Detailed Description—
Theory of Operation
The MAX1213 uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary ana-
log input terminals (INN) are centered around a com-
mon-mode voltage of 1.365V, and accept a differential
analog input voltage swing of ±V_FS / 4 each, resulting in
a typical differential full-scale signal swing of 1.454V_P-P.
Inputs INP and INN are buffered prior to entering each
T/H stage and are sampled when the differential sam-
pling clock signal transitions high.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1213 architecture.
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1213. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for
enhanced AC performance as the signals are progress-
ing through the analog stages. The MAX1213 analog
inputs are self-biased at a common-mode voltage of
1.365V and allow a differential input voltage swing of
1.454V_P-P (Figure 2). Both inputs are self-biased
INP
2.2kΩ
TO COMMON MODE
INP
AV_CC
INN
2.2kΩ
TO COMMON MODE
AGND
COMMON-MODE
VOLTAGE (1.365V)
INN
COMMON-MODE
VOLTAGE (1.365V)
Figure 2. Simplified Analog Input Architecture and Allowable
Input Voltage Range
through 2kΩ resistors, resulting in a typical differential
input resistance of 4kΩ. It is recommended to drive the
analog inputs of the MAX1213 in AC-coupled configu-
ration to achieve best dynamic performance. See the
Transformer-Coupled, Differential Analog Input Drive
section for a detailed discussion of this configuration.
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