MAX1144-MAX1145 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 14-Bit ADCs, 150ksps, 3.3V Single Supply

14-Bit ADCs, 150ksps, 3.3V Single Supply
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = 3.3V ±5%, f_SCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, V_REF =
2.048V, C_REF = 4.7µF, C_CREF = 1µF, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
Input Hysteresis
Input Capacitance
DIGITAL OUTPUTS
SYMBOL
V_HYST
C_IN
CONDITIONS
MIN TYP MAX UNITS
0.2
V
10
pF
Output High Voltage
V_OH
I_SOURCE = 0.5mA
DV_DD -
V
0.5
Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
V_OL
I_SINK = 5mA
I_SINK = 16mA
I_L
CS = DV_DD
CS = DV_DD
0.4
V
0.8
-10
+10
µA
10
pF
Analog Supply
Digital Supply
AV_DD
DV_DD
3.135 3.3 3.465
V
3.135 3.3 3.465
V
Analog Supply Current
I_ANALOG
Unipolar mode
Bipolar mode
SHDN = 0, or software power-down mode
3.9
8
mA
7
11
0.1
10
µA
Digital Supply Current
Unipolar or bipolar mode
I_{DIGITAL SHDN = 0, or software power-down mode}
1
2
mA
1.1
10
µA
Power-Supply Rejection Ratio
(Note 8)
PSRR AV_DD = DV_DD = 3.135V to 3.465V
65
dB
TIMING CHARACTERISTICS (Figures 5 and 6)
(AV_DD = DV_DD = 3.3V ±5%, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DIN to SCLK Setup
t_DS
DIN to SCLK Hold
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
C_LOAD = 50pF
C_LOAD = 50pF
SCLK High Pulse Width
t_CH
SCLK Low Pulse Width
t_CL
SCLK Fall to SSTRB
CS Fall to SSTRB Enable
CS Rise to SSTRB Disable
t_SSTRB
t_SDV
t_STR
C_LOAD = 50pF
C_LOAD = 50pF, external clock mode
C_LOAD = 50pF, external clock mode
SSTRB Rise to SCLK Rise
RST Pulse Width
t_SCK
t_RS
Internal clock mode
MIN TYP MAX UNITS
50
ns
0
ns
70
ns
80
ns
80
ns
100
ns
0
ns
120
ns
120
ns
80
ns
80
ns
80
ns
0
ns
278
70
ns
4 _______________________________________________________________________________________