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MAX1144-MAX1145 Datasheet, PDF (12/18 Pages) Maxim Integrated Products – 14-Bit ADCs, 150ksps, 3.3V Single Supply
14-Bit ADCs, 150ksps, 3.3V Single Supply
Table 3. Unipolar Full Scale and Zero
Scale
PART
MAX1144
MAX1145
ZERO SCALE
0
0
FULL SCALE
6 (VREF/2.048)
VREF
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 6 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1144/MAX1145 at clock rates up to 4MHz, pro-
vided the minimum acquisition time, tACQ, is kept
above 1.39µs in bipolar mode and 1.67µs in unipolar
mode. Data can be clocked out at 4MHz.
Output Data
The output data format is straight binary for unipolar
conversions and two’s complement in bipolar mode.
The MSB is shifted out of the MAX1144/MAX1145 first
in both modes.
Data Framing
The falling edge of CS does not start a conversion on the
MAX1144/MAX1145. The first logic high clocked into
DIN is interpreted as a start bit and defines the first bit of
the control byte. A conversion starts on the falling edge
of SCLK, after the seventh bit of the control byte (the P1
bit) is clocked into DIN. The start bit is defined as:
• The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after AVDD is
applied.
• The first high bit clocked into DIN after CS is pulsed
high then low.
If a falling edge on CS forces a start bit before the con-
version or calibration is complete, then the current
operation terminates and a new one starts.
Applications Information
Power-On Reset
When power is first applied to the MAX1144/MAX1145,
or if RST is pulsed low, the internal calibration registers
are set to their default values. The user-programmable
registers (P0, P1, and P2) are low, and the device is
configured for bipolar mode with internal clocking.
Calibration
Periodically calibrate the MAX1144/MAX1145 to com-
pensate for temperature drift and other variations. After
any change in ambient temperature more than +10°C,
the device should be recalibrated. A 100mV change in
supply voltage or any change in the reference voltage
should be followed by a calibration. Calibration cor-
Table 4. Bipolar Full Scale, Zero Scale,
and Negative Scale
PART
MAX1144
MAX1145
NEGATIVE FULL
SCALE
-6 (VREF/2.048)
-VREF
ZERO
SCALE
0
0
FULL SCALE
+6 (VREF/2.048)
+VREF
rects for errors in gain, offset, integral nonlinearity, and
differential nonlinearity.
The MAX1144/MAX1145 should be calibrated after
power-up or after the assertion of reset. Make sure the
power supplies and the reference voltage have fully
settled prior to initiating the calibration sequence.
Initiate calibration by setting M1 = 0 and M0 = 1 in the
control byte. In internal clock mode, SSTRB goes low at
the beginning of calibration and goes high to signal the
end of calibration, approximately 80,000 clock cycles
later. In external clock mode, SSTRB goes high at the
beginning of calibration and goes low to signal the end
of calibration. Calibration should be performed in the
same clock mode that is used for conversions.
Reference
The MAX1144/MAX1145 require an external reference.
The external reference must be bypassed with a 4.7µF
capacitor. The input impedance at REF is a minimum of
16kΩ for DC currents. During conversion, an external
reference at REF must deliver up to 150µA DC load
current and have an output impedance of 10Ω or less.
Analog Input
The MAX1144/MAX1145 use a capacitive DAC that
provides an inherent track/hold function. Drive AIN with
a source impedance less than 10Ω. Any signal condi-
tioning circuitry must settle with 14-bit accuracy in less
than 500ns. Limit the input bandwidth to less than half
the sampling frequency to eliminate aliasing. The
MAX1144/MAX1145 have a complex input impedance
that varies from unipolar to bipolar mode (Figure 1).
Input Range
The analog input range in unipolar mode is 0 to +6V for
the MAX1144, and 0 to +2.048V for the MAX1145. In
bipolar mode, the analog input can be -6V to +6V for
the MAX1144, or -2.048V to +2.048V for the MAX1145.
Unipolar or bipolar mode is programmed with the
UNI/BIP bit of the control byte. When using a reference
other than the suggested +2.048V, the full-scale input
range varies accordingly. The full-scale input range
depends on the voltage at REF and the sampling mode
selected (Tables 3 and 4).
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