MAX11212_12 Datasheet, PDF (4/14 Pages) Maxim Integrated Products – 18-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface

MAX11212
18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SCLK Rising Edge Data Hold
Time
t4 Allows for positive edge data read
3
ns
RDY/DOUT Fall to SCLK Rising
Edge
t5
Next Data Update Time; No Read
Allowed
t6
MAX11212A
MAX11212B
Data Conversion Time
MAX11212A
t7
MAX11212B
Data Ready Time After Calibration
Starts (CAL + CNV)
t8
MAX11212A
MAX11212B
SCLK High After RDY/DOUT
Goes Low to Activate Sleep Mode
t9
MAX11212A
MAX11212B
0
ns
155
Fs
169
8.6
ms
73
208.3
ms
256.1
0
8.6
ms
0
73
Time From RDY/DOUT Low
to SCLK High for Sleep Mode
Activation
MAX11212A
t10
MAX11212B
0
8.6
ms
0
73
Data Ready Time After Wake-Up
from Sleep Mode
MAX11212A
t11 _MAX11212B
Data Ready Time After Calibration
MAX11212A
from Sleep Mode Wake-Up (CAL
t12
+ CNV)
MAX11212B
8.6
ms
73
208.4
ms
256.2
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
4  
Maxim Integrated