MAX11212_12 Datasheet, PDF (3/14 Pages) Maxim Integrated Products – 18-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface

MAX11212
18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
REF Input Capacitance
15
pF
AIN Voltage Range
VAINP - VAINN
-VREF
+VREF
V
REF Voltage Range
VAVDD
V
Input Sampling Rate
MAX11212A
fS
MAX11212B
246
kHz
225
REF Sampling Rate
MAX11212A
MAX11212B
246
kHz
225
LOGIC INPUTS (SCLK, CLK)
Input Current
Input leakage current
±1
FA
Input Low Voltage
VIL
0.3 x
VDVDD
V
Input High Voltage
Input Hysteresis
External Clock
LOGIC OUTPUTS (RDY/DOUT)
Output Low Level
VIH
VHYS
MAX11212A
MAX11212B
VOL
IOL = 1mA; also tested for VDVDD =
3.6V
0.7 x
VDVDD
200
2.4576
2.2528
0.4
V
mV
MHz
V
Output High Level
VOH
IOH = 1mA; also tested for VDVDD =
3.6V
0.9 x
VDVDD
V
Floating State Leakage Current
Output leakage current
±10
FA
Floating State Output
Capacitance
9
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
Total Operating Current
AVDD + DVDD
DVDD Operating Current
AVDD Operating Current
AVDD Sleep Current
DVDD Sleep Current
2-WIRE SERIAL-INTERFACE TIMING CHARACTERISITCS
SCLK Frequency
fSCLK
SCLK Pulse Width Low
t1 60/40 duty cycle 5MHz clock
SCLK Pulse Width High
t2 40/60 duty cycle 5MHz clock
SCLK Rising Edge to Data Valid
Transition Time
t3
2.7
3.6
1.7
3.6
230
300
45
60
185
245
0.4
2
0.35
2
5
80
80
40
V
V
FA
FA
FA
FA
FA
MHz
ns
ns
ns
Maxim Integrated
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