MAX11202 Datasheet, PDF (4/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at T_A = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SCLK Rising Edge Data Hold
Time
SYMBOL
CONDITIONS
t4
Allows for positive edge data read
MIN TYP MAX UNITS
3
ns
RDY/DOUT Fall to SCLK Rising
Edge
t5
Next Data Update Time;
No Read Allowed
MAX11202A
t6
MAX11202B
Data Conversion Time
MAX11202A
t7
MAX11202B
Data Ready Time After Calibration
Starts (CAL + CNV)
t8
MAX11202A
MAX11202B
SCLK High After RDY/DOUT
Goes Low to Activate Sleep Mode
t9
MAX11202A
MAX11202B
Time from RDY/DOUT Low to
SCLK High for Sleep-Mode
Activation
MAX11202A
t10
MAX11202B
Data Ready Time After Wake-Up
from Sleep Mode
MAX11202A
t11
MAX11202B
Data Ready Time After Calibration
MAX11202A
from Sleep Mode Wake-Up (CAL
t12
+ CNV)
MAX11202B
0
ns
155
Fs
169
8.6
ms
73
208.3
ms
256.1
0
8.6
ms
0
73
0
8.6
ms
0
73
8.6
ms
73
208.4
ms
256.2
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: V_AINP = V_AINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
Note 6: The MAX11202A has no normal-mode rejection at 50Hz or 60Hz.
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