MAX11202 Datasheet, PDF(10/14 Page) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

◁

24-Bit, Single-Channel, Ultra-Low-Power, Delta

Sigma ADC with 2-Wire Serial Interface

2-Wire Interface

The MAX11202 is compatible with the 2-wire interface

and uses SCLK and RDY/DOUT for serial communica-

tions. In this mode, all controls are implemented by tim-

ing the high or low phase of the SCLK. The 2-wire serial

interface only allows for data to be read out through the

RDY/DOUT output. Supply the serial clock to SCLK to

shift the conversion data out.

The RDY/DOUT is used to signal data ready, as well as

reading the data out when SCLK pulses are applied.

RDY/DOUT is high by default. The MAX11202 pulls RDY/

DOUT low when data is available at the end of conver-

sion, and stays low until clock pulses are applied at the

SCLK input. On applying the clock pulses at SCLK, the

RDY/DOUT outputs the conversion data on every SCLK

positive edge. To monitor data availability, pull RDY/

DOUT high after reading the 24 bits of data by supplying

a 25th SCLK pulse.

The different operational modes using this 2-wire inter-

face are described in the following sections.

Data Read Following Every Conversion

The MAX11202 indicates conversion data availability, as

well as the retrieval of data through the RDY/DOUT out-

put. The RDY/DOUT output idles at the value of the last

bit read unless a 25th SCLK pulse is provided, causing

RDY/DOUT to idle high.

The timing diagram for the data read is shown in Figure

1. Once a low is detected on RDY/DOUT, clock pulses

at SCLK clock out the data. Data is shifted out MSB first

and is in binary twoâs complement format. Once all the

data has been shifted out, a 25th SCLK is required to

pull the RDY/DOUT output back to the idle high state.

See Figure 2.

If the data is not read before the next conversion data is

updated, the old data is lost, as the new data overwrites

the old value.

Data Read Followed by Self-Calibration

To initiate self-calibration at the end of a data read, pro-

vide a 26th SCLK clock pulse. After reading the 24 bits

of conversion data, a 25th positive edge on SCLK pulls

the RDY/DOUT output back high, indicating the end of

the data read. Provide a 26th SCLK clock pulse to initi-

ate a self-calibration routine starting on the falling edge

of the SCLK. A subsequent falling edge of RDY/DOUT

indicates data availability at the end of calibration. The

timing is illustrated in Figure 3.

Data Read Followed by Sleep Mode

The MAX11202 can be put into sleep mode to save

power between conversions. To activate the sleep mode,

idle the SCLK high any time after the RDY/DOUT output

goes low (that is, after conversion data is available). It is

not required to read out all 24 bits before putting the part

in sleep mode. Sleep mode is activated after the SCLK is

held high (see Figure 4). The RDY/DOUT output is pulled

high once the device enters sleep mode. To come out

of the sleep mode, pull SCLK low. After the sleep mode

is deactivated (when the device wakes up), conversion

starts again and RDY/DOUT goes low, indicating the

next conversion data is available (see Figure 4).

Single-Conversion Mode

For operating the MAX11202 in single-conversion mode,

activate and deactivate sleep mode between conver-

sions as described in the Data Read Followed by Sleep

Mode section). Single-conversion mode reduces power

consumption by shutting down the device when idle

between conversions. See Figure 4.

Single-Conversion Mode

with Self-Calibration at Wake-Up

The MAX11202 can be put in self-calibration mode imme-

diately after wake-up from sleep mode. Self-calibration at

wake-up helps to compensate for temperature or supply

changes if the device is shut down for extensive periods.

To automatically start self-calibration at the end of sleep

mode, all the data bits must be shifted out followed by

the 25th SCLK edge to pull RDY/DOUT high. On the 26th

SCLK, keep it high for as long as shutdown is desired.

Once SCLK is pulled back low, the device automatically

performs a self-calibration and, when the data is ready,

the RDY/DOUT output goes low. See Figure 5. This also

achieves the purpose of single conversions with self-

calibration.

▷