MAX11202 Datasheet, PDF (12/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
SCLK
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
1
2
3
t9
t10
D23
D22
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT
SLEEP MODE
24
SLEEP
MODE
1
2
D0
D23
D22
CONVERSION IS DONE
DATA IS AVAILABLE
t11
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing
SCLK
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
25TH SCLK PULLS RDY/DOUT HIGH
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT SLEEP MODE
AND STARTS CALIBRATION
1
2
3
t10
24
25
26
SLEEP
MODE
1
2
D23
D22
D0
D23
D22
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t12
Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up
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