DS1682 Datasheet, PDF (4/14 Pages) Dallas Semiconductor – Total Elapsed Time Recorder with Alarm

DS1682
Timing Diagram
Total-Elapsed-Time Recorder
with Alarm
SDA
tBUF
tF
tLOW
SCL
t_HD:STA
STOP START
t_R
tHD:DAT
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
tHIGH
tSU:DAT
tHD:STA
tSU:STA
REPEATED
START
tSP
tSU:STO
Note 1: Typical values are at T_A = +25°C, V_CC = 4.0V.
Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used sequentially, allowing up to 3 x
E_E. The configuration register, alarm trip-point register, and user memory use a single array, limiting them to one E_E.
Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended. A typical value is
0.01μF. V_CC must be maintained above V_CC minimum, including transients, during EEPROM writes.
Note 4: VCC must be at or above 2.5V for t_EW after the end of an event to ensure data transfer to the EEPROM.
Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 8: The maximum t_HD:DAT has only to be met if the device does not stretch the low period (t_LOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT ≥ 250ns must be met. This is
automatically the case if the device does not stretch the t_LOW. If such a device does stretch t_LOW, it must output the next
data bit to the SDA line t_R(MAX) + t_SU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
Note 10: C_B—Total capacitance of one bus line in pF.
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