MAX11311 Datasheet, PDF (35/51 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11311
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interrupt Mask Register (Read/Write)
BIT
0
1
2
3
4
5
8:6
11:9
14:12
15
FIELD NAME
ADCFLAGMSK
ADCDRMSK
ADCDMMSK
GPIDRMSK
GPIDMMSK
DACOIMSK
TMPINTMSK[2:0]
TMPEXT1MSK[2:0]
TMPEXT2MSK[2:0]
VMONMSK
DESCRIPTION
ADC flag interrupt mask
• Masks ADCFLAG interrupt bit when asserted.
• In ADC continuous-sweep mode, INT is asserted for 100nS at the end of each sweep
whether ADCFLAG interrupt is cleared or not.
• 1: Prevents the assertion of ADCFLAG interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCFLAG interrupt bit to pull INT low.
ADC data ready interrupt mask
• Masks ADCDR interrupt bit when asserted.
• 1: Prevents the assertion of ADCDR interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCDR interrupt bit to pull INT low.
ADC data missed interrupt mask
• Masks ADCDM interrupt bit when asserted.
• 1: Prevents the assertion of ADCDM interrupt bit from pulling INT low.
• 0: Allows the assertion of ADCDM interrupt bit to pull INT low.
GPI event ready interrupt mask
• Masks GPIDR interrupt bit when asserted.
• Supersedes the settings in the GPI IRQ Mode registers.
• 1: Prevents the assertion of GPIDR interrupt bit from pulling INT low.
• 0: Allows the assertion of GPIDR interrupt bit to pull INT low.
GPI event missed interrupt mask
• Masks GPIDM interrupt bit when asserted.
• Can be deasserted only if GPIDRMSK is deasserted.
• 1: Prevents the assertion of GPIDM interrupt bit from pulling INT low.
• 0: Allows the assertion of GPIDM interrupt bit to pull INT low.
DAC driver overcurrent interrupt mask
• Masks DACOI interrupt bit when asserted.
• 1: Prevents the assertion of DACOI interrupt bit from pulling INT low.
• 0: Allows the assertion of DACOI interrupt bit to pull INT low.
Internal temperature interrupt mask
• Masks TMPINT[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPINT[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPINT[i] interrupt bit to pull INT low (0≤i≤2).
1st external temperature interrupt mask
• Masks TMPEXT1[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPEXT1[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPEXT1[i] interrupt bit to pull INT low (0≤i≤2).
2nd external temperature interrupt mask
• Masks TMPEXT2[2:0] interrupt bits when asserted on a bit-by-bit basis.
• 1: Prevents the assertion of TMPEXT2[i] interrupt bit from pulling INT low (0≤i≤2).
• 0: Allows the assertion of TMPEXT2[i] interrupt bit to pull INT low (0≤i≤2).
High-voltage supply monitor mask
• Masks VMON interrupt bit when asserted.
• 1: Prevents the assertion of VMON interrupt bit from pulling INT low.
• 0: Allows the assertion of VMON interrupt bit to pull INT low.
www.maximintegrated.com
Maxim Integrated │  35