MAX11311 Datasheet, PDF (27/51 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11311
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
SPI transactions are made of a minimum of three bytes.
Each transaction is defined by the assertion of CS. The
first byte contains the address and the read/write bit. The
second byte carries the most significant byte of the data
to either write or read. The third byte contains the least
significant byte of the data to either write or read. Such a
transaction is shown in Table 1. For write transactions, the
targeted register content is modified only after the third
byte has been fully received. The bits come out of DOUT
(or come in DIN), most significant bit first.
Note that the duration of the transaction is determined
by the assertion of CS. If CS remains asserted past the
third byte, and if SCLK remains active past the third byte,
the MAX11311 assumes that a second data sample is
received (or transmitted) corresponding to the next register
address. The address keeps on incrementing as CS
remains asserted and SCLK remains active. Table 2
shows an example of such a burst transaction.
Each time a new data sample is read or written, the register
address is incremented by one until it reaches the last
register address.
If a transaction targets an unused address, nothing is
written within the MAX11311 for write transactions, and
all zeros are read back for read transactions. Similarly, if
Table 1. Single Register SPI Transaction
Format
B7 B6 B5 B4 B3 B2 B1 B0
1st Byte
Address[6:0]
R/WB
2nd Byte
Data[15:8]
3rd Byte
Data[7:0]
a write transaction targets a read-only register, nothing is
written to the device.
Burst Transaction Address
Incrementing Modes
With a burst transaction, the address of the initial register
is entered once. The data of the targeted register can then
be written or read. If the serial clock keeps running, and if
CS remains asserted, the device increments the address
pointer and writes or reads the next data after the next
16 serial clock periods. This scheme goes on until CS is
deasserted.
There are two address incrementing modes. In one mode,
the address is simply incremented by one (default mode),
while in the other, the address is incremented contextually.
When writing DAC data registers in a burst fashion using
contextual addressing, the host would write the address
of the first port that is DAC-configured (starting from the
lowest port index). As CS remains asserted and another
set of 16 serial clock cycles are received, the next DAC-
configured port is written. This scheme continues until the
last DAC-configured port is reached. At that point, any
additional serial clock cycle results in looping back to the
first DAC-configured port.
The contextual addressing scheme is only valid for writing
DAC data registers, as described above, and reading
ADC data registers.
Interrupt Operations
The MAX11311 issues interrupts to alert the host of various
events. All events are recorded by the interrupt register.
The assertion of an interrupt register bit results in the
assertion of the interrupt port (INT) if that interrupt bit is
Table 2. Multiple Register SPI Transaction Format
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte
7th Byte
8th Byte
9th Byte
10th Byte
11th Byte
B7
B6
B5
B4
B3
B2
B1
Address_N[6:0]
Data_N[15:8]
Data_N[7:0]
Data_N+1[15:8]
Data_N+1[7:0]
Data_N+2[15:8]
Data_N+2[7:0]
Data_N+3[15:8]
Data_N+3[7:0]
Data_N+4[15:8]
Data_N+4[7:0]
B0
R/WB
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