MAX11311 Datasheet, PDF (32/51 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11311
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Register Detailed Description
Device ID Register (Read)
BIT FIELD NAME
Device ID
15:0
DEVID[15:0] ^{• 0000_0100_0010_0100}
DESCRIPTION
Interrupt Register (Read)
BIT FIELD NAME
DESCRIPTION
ADC flag interrupt
• Asserted when the ADC completes a conversion (ADC set in single-conversion mode) or when
0
ADCFLAG
the ADC completes a sweep (ADC set in single-sweep or continuous-sweep mode).
• No interrupt is generated when the ADC is in idle mode.
• Cleared after the interrupt register is read.
ADC data ready interrupt
• Asserted when any ADC data register receives a new data sample. If a port is configured to
average 2^N samples, it takes 2^N sweeps for that port data register to be refreshed and assert
ADCDR.
1
ADCDR
• Data registers are refreshed either at the end of a conversion (ADC set in single-conversion
mode) or at the end of a sweep (ADC set in single-sweep or continuous-sweep mode).
• Cleared after the interrupt register is read, and after both ADCST[10:0] and ADCST[11] registers
are read subsequently.
ADC data missed interrupt
• Asserted when the host missed reading a port’s ADC data register by the time that port’s ADC
2
ADCDM
data register is overwritten by new data.
• Cleared after the interrupt register is read.
GPI event ready interrupt
• Asserted when a new event is captured by GPI-configured ports. The type of event is set by the
3
GPIDR
corresponding GPI IRQ mode register. The host can then consult GPIST[10:0] and GPIST[11]
registers to identify the port that caused the interrupt.
• Cleared after the interrupt register is read, and after both GPIST[10:0] and GPIST[11] are read
subsequently.
GPI event missed interrupt
• Asserted when the host missed reading the GPI status register by the time that register is
overwritten.
4
GPIDM
• Must be used in conjunction with GPIDR for proper operation.
• Cleared after the interrupt register is read, and after both GPIST[10:0] and GPIST[11] are read
subsequently.
DAC driver overcurrent interrupt
• Asserted when the DAC driver current exceeds approximately 50mA. The host can then read
5
DACOI
DACOIST[10:0] and DACOIST[11] to identify the port that caused the interrupt.
• Cleared after the interrupt register is read, and after both DACOIST[10:0] and DACOIST[11]
registers are read subsequently.
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