MAX16050 Datasheet, PDF (3/22 Pages) Maxim Integrated Products – Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability

Voltage Monitors/Sequencer Circuits with
Reverse-Sequencing Capability
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = 2.7V to 13.2V, V_EN = V_ABP, T_A = T_J = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DELAY, TIMEOUT Output Source
Current
I_DT
V_DELAY = V_TIMEOUT = 0V
1.7
2.5
3.0
µA
DELAY, TIMEOUT Threshold
Voltage
V_{TH_DT}
1.218 1.250 1.281
V
DIGITAL INPUTS/OUTPUTS
SHDN, FAULT, EN_HOLD Input-
Logic Low Voltage
SHDN, FAULT, EN_HOLD Input-
Logic High Voltage
EN_HOLD Input Current
EN_HOLD to OUT Delay
FAULT, SHDN to ABP Pullup
Resistance
SHDN to OUT_ Delay
RESET Output Low Voltage
REM, FAULT Output Low Voltage
FAULT Pulse Width
SET_ to FAULT Delay Time
V_IL
V_IH
I_I
t_{EN_OUT}
R_P
t_OUT
V_OL
V_{OL_RF}
t_{FAULT_PW}
t_{SET_FAULT}
V_CC = 3.3V, I_SINK = 3.2mA
V_CC = 1.8V, I_SINK = 100µA
V_CC = 3.3V, I_SINK = 3.2mA
SET_ falling below respective threshold
SEQ1–SEQ3 Logic-High Level
V_{IH_SEQ} MAX16050 only
0.4
V
2
V
1
µA
3
µs
60
100 160
kΩ
12
µs
0.3
V
0.3
0.3
V
1.9
µs
2.5
µs
V_ABP -
0.35
V
SEQ1–SEQ3 Logic High-
Impedance (No Connect) Level
SEQ1–SEQ3 Logic-Low Level
SEQ1–SEQ3 High-Impedance
State Tolerance Current
RESET CIRCUIT
RESET, REM, OV_OUT Output
Leakage
RESET Timeout Period
OUT_, FAULT, SHDN to RESET
Delay
V_{IX_SEQ} MAX16050 only
V_{IL_SEQ} MAX16050 only
I_IX
MAX16050 (Note 3)
I_LKG
t_RP
t_RST
V_RESET = V_REM = V_{OV_OUT} = 5V
TIMEOUT = ABP
TIMEOUT = unconnected
0.92
1.45
V
0.33
V
-6
+6
µA
1
µA
50
128 300
ms
3
µs
CHARGE-PUMP OUTPUT
CP_OUT Voltage
V_{CP_OUT} I_{CP_OUT} = 0.5µA
V_CC + V_CC + V_CC +
V
4.6
5
5.8
CP_OUT Source Current
I_{CP_OUT} V_{CP_OUT} = V_CC + 2V
17
25
30
µA
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at T_A =
+25°C and T_A = +85°C. Specifications at T_A = -40°C are guaranteed by design.
Note 2: When the voltage is below the V_UVLO and above V_CCR, OUT_ and RESET are asserted low.
Note 3: SEQ1–SEQ3 are inputs with three logic levels: high, low, and high-impedance.
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