MAX1011 Datasheet, PDF (3/12 Pages) Maxim Integrated Products – Low-Power, 90Msps, 6-Bit ADC

Low-Power, 90Msps, 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS
(V_CC = +5V ±5%, V_CCO = 3.3V ±300mV, T_A = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), V_IN = 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
Maximum Sample Rate
Analog Input -0.5dB Bandwidth
Effective Number of Bits
Signal-to-Noise Plus Distortion
Ratio
f_MAX
BW
ENOB_M
ENOB_H
ENOB_L
SINAD
GAIN = GND, open, V_CC
GAIN = open (mid gain)
GAIN = open (mid gain), f_IN = 50MHz,
-1dB below full scale
GAIN = V_CC (high gain)
GAIN = GND (low gain)
GAIN = open (mid gain)
90
55
5.6
5.85
5.7
5.8
5.85
35.5
37
Input Offset (Note 5)
OFF Guaranteed by design
TIMING CHARACTERISTICS (Data outputs: R_L = 1MΩ, C_L = 15pF)
Clock to Data Propagation
Delay
t_PD
(Note 6)
-0.5
0.5
3.0
Data Valid Skew
t_SKEW (Note 6)
1
Input to DCLK Delay
t_DCLK TNK+ to DCLK (Note 6)
4.5
Aperture Delay
t_AD
Figure 8
5.5
Pipeline Delay
PD Figure 8
1
UNITS
Msps
MHz
Bits
dB
LSB
ns
ns
ns
ns
clock
cycle
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in V_CC supply voltage,
expressed in decibels.
Note 4: The current in the V_CCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at compensation inputs (Figures 2 and 3).
Note 6: t_PD and t_SKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t_DCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
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