DS1337_09 Datasheet, PDF (3/16 Pages) Maxim Integrated Products – I2C Serial Real-Time Clock

DS1337 I²C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(V_CC = 1.8V to 5.5V, T_A = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
SCL Clock Frequency
f_SCL
Fast mode
Standard mode
100
0
Bus Free Time Between a
STOP and START Condition
t_BUF
Fast mode
Standard mode
1.3
4.7
Hold Time (Repeated)
START Condition (Note 10)
t_HD:STA
Fast mode
Standard mode
0.6
4.0
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
(Notes 11, 12)
Data Setup Time (Note 13)
Rise Time of Both SDA and
SCL Signals (Note 14)
Fall Time of Both SDA and
SCL Signals (Note 14)
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_R
t_F
t_SU:STO
C_B
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 14)
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C_B
20 + 0.1C_B
20 + 0.1C_B
20 + 0.1C_B
0.6
4.0
I/O Capacitance (SDA, SCL)
C_I/O
(Note 15)
Oscillator Stop Flag (OSF)
Delay
t_OSF
100
MAX
400
100
UNITS
kHz
s
s
s
s
s
0.9
s
ns
300
1000
ns
300
300
ns
s
400
pF
10
pF
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA, INTA, and SQW/INTB.
I_CCA—SCL clocking at max frequency = 400kHz, V_IL = 0.0V, V_IH = V_CC.
Specified with the I²C bus inactive, V_IL = 0.0V, V_IH = V_CC.
SQW enabled.
Specified with the SQW function disabled by setting INTCN = 1.
Using recommended crystal on X1 and X2.
The device is fully accessible when 1.8  V_CC  5.5V. Time and date are maintained when 1.3V  V_CC  1.8V.
After this period, the first clock pulse is generated
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t_HD:DAT need only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT  to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t_{R max} + t_SU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
C_B—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
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